From helmut.zulus at pcl.at  Fri Jul  6 09:12:28 2007
From: helmut.zulus at pcl.at (Helmut Zulus)
Date: Fri, 06 Jul 2007 09:12:28 +0200
Subject: [diycalculator_hw_dev] sometimes you have luck...
In-Reply-To: <000601c7b81a$6f978550$0401a8c0@maxt60p>
References: <000601c7b81a$6f978550$0401a8c0@maxt60p>
Message-ID: <468DEB5C.60806@pcl.at>

Last night I occasionally found a tiny little bug, which Johannes and me 
were hunting for several weeks (months) now.

In some very special cases, certain opcodes, especially more complicated 
ones, like BCD instructions and certain settings of the user adjustable 
CPU clock divider, caused the CPU to malfunction.
Not only wrong results on calculations with "Joe's BCD Routines" but 
also very unpredictable results of the synthesizer tools. For no obvious 
reason, minor changes in the VHDL sources could render the DIY 
Calculator not to work at all.

Long story's easy solution:
The CPU runs on a two phase clock (12.5MHz, CLK1 and 180degrees shifted 
CLK2). The input databus was latched by sysCLK (25MHz) and the read 
strobe. This caused the databus to be latched twice.
After gating the latch enable signal with the appropriate clock phase, 
everything works perfect.

Further debugging can continue now !

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