[diycalculator_hw_bug] [Bug 36] New: rework the flag processing inside the CPU

[PCL_bugzilla-daemon at printed.inbus.at]

http://svn.pcl.at/bugzilla/show_bug.cgi?id=36

           Summary: rework the flag processing inside the CPU
           Product: DIY Calculator Hardware Project
           Version: 1.0
          Platform: All
        OS/Version: All
            Status: NEW
          Severity: critical
          Priority: P1
         Component: FPGA VHDL
        AssignedTo: johannes.hausensteiner at pcl.at
        ReportedBy: johannes.hausensteiner at pcl.at
         QAContact: diycalculator_hw_bug at printed.inbus.at


The way the flag update (carry, zero, etc.) is currently implemented inside the
CPU VHDL code places a large burdon on the place and route tool. Sometimes the
timing constraints cannot be met, sometimes it simply does not work. So a
redesign of the flag processing seems the best solution.


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