From PCL_bugzilla-daemon at printed.inbus.at Fri Aug 31 13:35:40 2007
From: PCL_bugzilla-daemon at printed.inbus.at (PCL_bugzilla-daemon at printed.inbus.at)
Date: Fri, 31 Aug 2007 13:35:40 +0200 (CEST)
Subject: [diycalculator_hw_bug] [Bug 36] New: rework the flag processing
inside the CPU
Message-ID:
http://svn.pcl.at/bugzilla/show_bug.cgi?id=36
Summary: rework the flag processing inside the CPU
Product: DIY Calculator Hardware Project
Version: 1.0
Platform: All
OS/Version: All
Status: NEW
Severity: critical
Priority: P1
Component: FPGA VHDL
AssignedTo: johannes.hausensteiner at pcl.at
ReportedBy: johannes.hausensteiner at pcl.at
QAContact: diycalculator_hw_bug at printed.inbus.at
The way the flag update (carry, zero, etc.) is currently implemented inside the
CPU VHDL code places a large burdon on the place and route tool. Sometimes the
timing constraints cannot be met, sometimes it simply does not work. So a
redesign of the flag processing seems the best solution.
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From PCL_bugzilla-daemon at printed.inbus.at Fri Aug 31 13:35:48 2007
From: PCL_bugzilla-daemon at printed.inbus.at (PCL_bugzilla-daemon at printed.inbus.at)
Date: Fri, 31 Aug 2007 13:35:48 +0200 (CEST)
Subject: [diycalculator_hw_bug] [Bug 36] rework the flag processing inside
the CPU
In-Reply-To:
Message-ID: <20070831113548.A281F58597@printed.inbus.at>
http://svn.pcl.at/bugzilla/show_bug.cgi?id=36
johannes.hausensteiner at pcl.at changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |ASSIGNED
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